As semiconductor chips begin to integrate more and more diversified functional blocks, power supply provisioning and power supply distribution on the chips become more and more challenging. High speed and high performance functional blocks generally consume substantial amounts of power. Some high speed and high performance functional blocks may need to minimize their voltage drops with respect to their power supply to operate, for example, at peak efficiency. Especially in an environment in which the voltage level of a power supply to a chip scales down, the demand for greater amounts of power may result in higher electrical currents which, in turn, may result to the undesirable effect of higher voltage drops on, for example, highly resistive, thin metal layers of the integrated circuit (IC) chip. In addition, as the chip scales down, the tolerances or allowable variations in the voltage drops also decreases.
The integration of analog functional blocks and digital function blocks on the same chip may also provide further challenges. Analog blocks tend to be typically sensitive to noise. Thus, the routing of metal layers carrying noisy electrical signals (e.g., noisy digital signals to and from digital functional blocks) or noisy power supply voltages and noisy power ground voltages may have detrimental effects on nearby analog functional blocks.
FIG. 9 shows a simplified block diagram of a die 10 that includes, for example, two analog functional blocks 20, a digital functional block 30 and wire-bond pads 40. In the simplified block diagram, only a few of the components are shown for illustration purposes and their disposition in the die 10 is merely for illustration purposes. The analog blocks are disposed near the edge of the die 10 to access their power supply interfaces and their signal interfaces. The proximity between the analog functional blocks 20 and their interfaces on the edge of the die 10 avoids interference resulting from other function blocks such as, for example, the digital function block 30. In addition, the proximity between the analog functional blocks 20 and their interfaces reduces the amount of voltage drop, for example, from a nearby wire-bond pad supplying a power supply voltage.
FIG. 9 also illustrates a design problem with respect to the digital functional block 30. The digital functional block 30 also needs to connect to at least one of the wire-bond pads 40. However, due to the sensitivity of the analog functional blocks 20, options may be limited. For example, the digital functional block 30 can not simply connect via a chip metal layer, for example, to wire-bond pad 40A or wire-bond pad 40B. In some implementations, the chip metal layer would pass right over an analog functional block 20A, 20B or would pass by a nearby analog functional block 20A, 20B (e.g., through the spatial gap between the analog functional blocks 20A, 20B) in connecting to the wire-bond pad 40A, 40B. The interference and noise from the chip metal layer would detrimentally affect the analog functional blocks 20A, 20B. In other possible implementations, the chip metal layer might pass by nearby analog functional blocks (e.g., analog functional blocks 20A, 20B), which increases interference, over a longer line path, which increases voltage drop, to the wire-bond pads (e.g., wire-bond pads 40C, 40D). In yet another possible implementation, the chip metal layer might pass over an even longer line path which further increases voltage drop to the wire-bond pads (e.g., wire-bond pad 40E).
Currently, one of the approaches is to use “flipchip” packaging. However, such an approach has proven to be a rather costly solution.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with some embodiments according to some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.